1. Field of the Invention
The invention relates to CMOS logic circuit, and more particularly to CMOS logic circuit having a reduced delay time and thus being capable of having a higher operation speed.
2. Description of the Related Art
For the purpose of accomplishing a high performance in a MOS integrated circuit, a threshold voltage has been conventionally controlled in a MOS transistor through a circuit. Specifically, it is possible to enhance an operation speed due to an increased driving ability and reduce electric consumption due to a reduction in a leakage current by lowering a threshold voltage while the MOS transistor is in operation, and raising a threshold voltage while the MOS transistor is not in operation.
For instance, Japanese Patent Publication No. 61-61260 published on Dec. 24, 1986 has suggested a circuit for generating such a voltage for biasing a substrate therewith so that a circuit operates most efficiently.
With rapid development in fabricating a semiconductor integrated circuit in a smaller size, it is absolutely necessary to lower a power voltage in order to ensure reliability in operation of the MOS transistor. Consequently, since it is necessary for a high performance MOS transistor which operates at a relatively low voltage, to arrange a threshold voltage in accordance with a scaling rule, it is quite important to reduce leakage current between source and drain regions in a weak inversion region of the MOS transistor.
In order to solve this problem, Japanese Unexamined Patent Publication No. 7-95032 published on Apr. 7, 1995 has suggested CMOS invertor circuit for reducing a leakage current between source and drain regions in a weak inversion region in a MOS transistor. The suggested CMOS invertor is said to be suitable for a device which operates at a relatively low voltage. The suggested circuit includes, as well as CMOS invertor, a first NMOS transistor having a gate electrically connected to an input terminal, a source electrically connected to a ground potential, and a drain electrically connected to a substrate of a second NMOS transistor constituting the CMOS invertor. The suggested circuit further includes a coupling capacitor electrically connected between the input terminal and a substrate of the first NMOS transistor. When an input voltage applied to the CMOS invertor is lower than a threshold voltage of the first NMOS transistor, a negative voltage is applied to a substrate of the second NMOS transistor by virtue of the coupling capacitor, resulting in that a threshold voltage being made higher.
Japanese Unexamined Patent Publication No. 63-229848 published on Sep. 26, 1988 has suggested a semiconductor memory device for reducing a sub-threshold leakage current without reduction in writing and reading-out speed and degradation of a device, by utilizing a variation in a threshold voltage caused by a variation in a potential at a substrate of a MOS transistor. Specifically, a substrate potential of a MOS transfer gate transistor is arranged deep while data is being held in the transistor, whereas a substrate potential is arranged shallow only when data is written into or is read out of the transistor.
Japanese Unexamined Patent Publication No. 57-78165 published on May 15, 1982, which is based on the United States application No. 164284 filed on Jun. 30, 1980, has suggested a circuit for biasing a substrate of a metal-oxide-semiconductor (MOS) integrated circuit, in particular, for biasing a substrate of a random access memory (RAM).
Japanese Unexamined Patent Publication No. 57-103346 has suggested a metal-oxide-semiconductor (MOS) integrated circuit including a self-advancing oscillator, a drive circuit receiving an output generated from the self-advancing oscillator, an AC coupling capacitor electrically connected to the drive circuit, and first and second MOS transistors coupled to each other through a diode. The first MOS transistor makes level-changes, and the second MOS transistor absorbs electric charges to thereby generate a voltage for biasing a substrate therewith. The drive circuit is comprised of third, fourth and fifth MOS transistors connected in series between a power source and a ground. Each of the third and fourth MOS transistors has a gate electrode which receives an output generated from the self-advancing circuit, and the fifth MOS transistor has a gate electrode which receives a reference voltage which is not dependent on a power voltage.
Japanese Unexamined Patent Publication No. 58-2061 has suggested CMOS integrated circuit including p-type MOSFET and n-type MOSFET wherein a potential of a substrate of the p-type MOSFET is set higher than a positive potential of a power source, and a potential of a substrate of the n-type MOSFET is set lower than a negative potential of the power source.
Japanese Unexamined Patent Publication No. 62-30421 published on Feb. 9, 1987 has suggested MOS integrated circuit including a MOS transistor having a source electrode, a back gate electrode, and a drain electrode, and an amplifier having a gain of almost one time. The source electrode of the MOS transistor is electrically connected to an input of the amplifier, and the back gate electrode of MOS transistor is electrically connected to an output of the amplifier.
Japanese Patent Publication No. 62-50984 published on Oct. 28, 1987, which is based on the West German application No. 2812378.6 filed on Mar. 21, 1978, has suggested a semiconductor circuit including at least two field effect transistors formed in a semiconductor crystal. The field effect transistors have source and drain regions both having a first electrical conductivity which are surrounded by semiconductor crystal regions having a second electrical conductivity. A voltage generator including an oscillator and a threshold voltage detector applies an auxiliary voltage between the semiconductor crystal regions and a ground potential. The auxiliary voltage is applied to a certain section of the semiconductor circuit through a pump circuit formed at an output terminal of the voltage generator.
Japanese Unexamined Patent Publication No. 63-40358 published on Feb. 20, 1988 has suggested a semiconductor device including, a MOS transistor, a bipolar transistor, a circuit for generating a substrate potential, a comparator circuit for comparing a reference threshold voltage of the MOS transistor to a predetermined reference voltage, an oscillator circuit for emitting an AC output voltage which is varied in accordance with an output generated from the comparator circuit, a rectifier circuit for rectifying an output generated from the oscillator circuit to thereby turn to a DC potential, and a controller for controlling the substrate potential in accordance with an output generated from the rectifier circuit to thereby control a threshold voltage of the MOS transistor.
Japanese Unexamined Patent Publication No. 5-211291 published on Aug. 20, 1993 has suggested a semiconductor integrated circuit device including a circuit for generating a bias voltage to bias a substrate therewith, having a plurality of CMOS invertors and a pump circuit. The bias voltage generating circuit includes a first circuit for applying a first substrate bias voltage to a semiconductor substrate, and a second circuit for applying a second substrate bias voltage to a semiconductor region having an electrical conductivity opposite to that of the semiconductor substrate.
In the above-mentioned various conventional circuits for controlling a voltage at a substrate, it is most preferable to control a voltage in such a manner that a threshold voltage is set lower for each of the transistors constituting a semiconductor integrated circuit while the semiconductor integrated circuit is in operation, and is set higher while the semiconductor integrated circuit is not in operation.
FIG. 1 illustrates a typical structure of CMOS invertor circuit for controlling a voltage at a substrate in a semiconductor integrated circuit. The illustrated circuit includes PMOS transistor 110, NMOS transistor 120, a first switch 130 for electrically connecting PMOS transistor 110 to either a first power voltage VDD0 or a second power voltage VDD1, and a second switch 140 for electrically connecting NMOS transistor 110 to either a first ground GND0 or a second ground GND1. The first and second switches 130 and 140 receive control signals S by which the switches 130 and 140 are controlled as to whether PMOS and NMOS transistors 110 and 120 are electrically connected to VDD1 or VDD0, or GND0 or GND1, respectively. Gates of PMOS transistor 110 and NMOS transistor 120 are electrically connected to each other, and similarly, drains of PMOS transistor 110 and NMOS transistor 120 are electrically connected to each other. An input signal IN1 is introduced to the thus electrically connected gates, and an output signal OUT1 is generated from the thus electrically connected drains.
Those skilled in the art would readily understand that if a voltage at a substrate is controlled in the above-mentioned manner, a problem would be caused that a circuit for controlling a substrate voltage could not avoid becoming larger in size due to an arrangement of a power source for generating a bias voltage, and separation of a substrate in each of the transistors, an arrangement of switches for switching substrate voltages, and an arrangement of switch control lines would be required.
In addition, it would be necessary to control a switch in each of the transistors for switching a substrate voltage in accordance with whether transistors constituting a semiconductor integrated circuit operate or do not operate. Furthermore, this control has to be carried out in real time. Hence, a circuit for controlling a substrate voltage cannot avoid requiring complicated control.